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impact可以下载,但是chioscope不能,rom教程。求助

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新青年lc 发表于 2019-8-25 16:29:53 | 显示全部楼层 |阅读模式

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求助:
       我是照着《黑金sparten6开发板berilog教程v1.6》进行第十部分,ROM,的学习,在下载完后,进行编译调试过程中,我在ise中直接打开chioscope,点击open cable后有时出现芯片,有时不出现芯片,但是接下来的结果都是如下:


1.
COMMAND: open_cable
INFO: Started ChipScope host (localhost:50001)
INFO: Successfully opened connection to server: localhost:50001 (localhost/127.0.0.1)
INFO: Successfully opened Digilent USB JTAG Cable
INFO: Cable: Digilent JTAG-HS1, Port: 0, Speed: 10000000 Hz
INFO: Found 0 Core Units in the JTAG device Chain.
INFO: If cores were expected to be found, see Answer Record 19337.


或者:

2.
COMMAND: configure 0 "D:\study\fpga\XC65LX45-2CSG324\AX545.170526\AX545.170526\AX545\09_VERILOG\10_rom_test\rom_test.bit" 0 import_inserter_cdc "" ""  doClean
INFO: Found 0 Core Units in the JTAG device Chain.
INFO: If cores were expected to be found, see Answer Record 19337.

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